1. Field of the Invention
The invention relates generally to audio amplification systems, and more particularly to systems and methods for converting data streams having a first sample rate to a second sample rate, wherein the input data streams are received in a packetized or bursty fashion.
2. Related Art
Pulse Width Modulation (PWM) or Class D signal amplification technology has existed for a number of years. PWM technology has become more popular with the proliferation of Switched Mode Power Supplies (SMPS). Since this technology emerged, there has been an increased interest in applying PWM techniques in signal amplification applications as a result of the significant efficiency improvement that can be realized through the use of Class D power output topology instead of the legacy (linear Class AB) power output topology.
Early attempts to develop signal amplification applications utilized the same approach to amplification that was being used in the early SMPS. More particularly, these attempts utilized analog modulation schemes that resulted in very low performance applications. These applications were very complex and costly to implement. Consequently, these solutions were not widely accepted. Prior art analog implementations of Class D technology have therefore been unable to displace legacy Class AB amplifiers in mainstream amplifier applications.
Recently, digital PWM modulation schemes have surfaced. These schemes use Sigma-Delta modulation techniques to generate the PWM signals used in the newer digital Class D implementations. These digital PWM schemes, however, did little to offset the major barriers to integration of PWM modulators into the total amplifier solution. Class D technology has therefore continued to be unable to displace legacy Class AB amplifiers in mainstream applications.
In a digital amplification system, audio data is usually transferred through a dedicated serial interface (SAI), SPDIF receiver, or DSP/host interface. An SAI interface provides a dedicated “LRCK” signal for frame synchronization and to indicate the sample rate. SPDIF data is biphase-mark encoded. Subframe and sample rate information may be recovered fairly easily by examining the preambles.
A DSP/host interface may, on the other hand, transmit data in a bursty manner, either as packetized data or as a straight FIFO write. To convey sample rate and channel information, time stamps and other information may be encoded in the packet header or such information may be passed in the commands, so that sample rate clock may be recovered by dedicated hardware clock recovery circuitry. One problem with this is that recovering the clock using time stamps and generating a low jitter clock from it is not a trivial design task.